Integrated circuit (“IC”) chips are becoming more densely packed with millions of electronic components. In order to manufacture various IC chips for specific applications, new technologies have been developed to satisfy the requirements of these chips. Each technology typically requires a set of specifications, such as voltage and frequency requirements. With the increasing number of semiconductor technologies in recent years, industries and/or IEEE have adopted various standards to facilitate communications between various chips. For example, when multiple chips are mounted on a printed circuit board (“PCB”), it is critical to understand what standard each chip follows so that they can properly communicate with each other. However, with the increasing number of standards on a single PCB, testing a PCB with various IC chips becomes more difficult.
A conventional test mechanism used in the past for testing a PCB is the boundary-scan testing. For example, IEEE 1149.1 supports testing of interconnections between IC pins. Scan test is typically performed by various scan circuits, also known as scan cells. Scan cells are usually located at the edge of the chip and they typically only perform testing functions. As such, it is advantageous to design scan cells as efficiently as possible because they don't typically contribute to the general functions of the chip. Scan cells generally include various comparators, which may be used to receive and to identify input signals.
Comparators are widely used in a variety of electronic equipment to compare the voltages of two analog inputs and to provide a digital output. A conventional comparator is an amplifier with a positive and a negative input, which typically has high input impedance. A comparator usually has high gain and produces an output signal that is the amplified difference of the positive and negative input signals. In general, a conventional comparator can be used to determine if an input signal is logically above or below a reference voltage. To enhance the noise immunity for the comparator, a technique of using hysteresis is often employed to reduce the effect of noise.
A hysteresis threshold typically defines the difference between “no input” and “input.” The terms of hysteresis threshold, hysteresis offset, hysteresis offset voltage, and/or hysteresis voltage can be used interchangeably herein. A hysteresis comparator typically switches its output to one output state when the input is above one level and switches to the opposite output state when the input is below a lower level, and the output does not switch at any intermediate level.
FIG. 1 shows a schematic diagram of a conventional comparator 100 having a hysteresis offset voltage. Comparator 100 includes a comparing circuit 104 and an element 102, which generates a hysteresis offset Vhyst. The use of hysteresis can reduce an unwanted response to small signal noise. Typically, comparing circuit 104 outputs an output signal in response to input signals at input terminal In1-In2 and a hysteresis offset which is provided by element 102.
FIG. 2 is a schematic diagram of a device 200 for a conventional method of creating a hysteresis offset voltage. Device 200 includes two identical n- or n-type transistors N3–4, resistors R1–2, and current sources S3–4. If the values of transistors, resistors, and current sources are properly sized, a desirable hysteresis offset can be created across the resistor R2. Once the hysteresis offset is created, the device 200 may discard some small input signals at terminals 206–208 according to the value of the hysteresis offset.
A problem with the conventional hysteresis comparator is that it takes too many components, such as two transistors, two resistors and two current sources, to generate a hysteresis offset. Another problem with the conventional hysteresis comparator is that it is difficult to adapt new and/or different standards because each standard may require a different hysteresis offset or hysteresis delay.
Thus, it would be desirable to have a comparator that is capable of generating selectable hysteresis offsets and hysteresis delays.